1. Field of the Invention
The present invention relates to a semiconductor apparatus equipped with a memory element and a method for manufacturing the same. In particular, the present invention relates to a semiconductor device equipped with a memory element having its improved electrical characteristics and a method for manufacturing the same.
2. Description of the Related Art
Among semiconductor devices, there is a memory type semiconductor device called a flash memory. As described in Jpn. Pat. Appln. KOKAI Publication No. 2002-261097, a memory element (memory cell) in a flash memory generally has a structure described below.
A source region and a drain region composed of impurity diffusion layers are provided at the top layer portion of a semiconductor substrate. A tunnel insulation film is provided on the surface of the semiconductor substrate while covering these source region and drain region. In addition, provided on the tunnel insulation film is a stacked gate structure including a floating gate electrode, an inter-electrode insulation film, and a control gate electrode. The stacked gate structure (floating gate electrode) is provided above an intermediate portion of the source region and the drain regions so as to be sandwiched therebetween.
Electrons or positive holes are accumulated on the floating gate electrode, and then, a threshold voltage of a transistor thereof is varied, whereby the memory cell is set in an electrically different state. In this manner, the memory cell develops a memory function. In order to accumulate electrons or positive holes on the floating gate electrode, a high voltage is applied to the control gate electrode to apply a high electric field to the tunnel insulation film. As a result, a tunnel current flows in the tunnel insulation film, so that electrons or positive holes are accumulated on the floating gate electrode.
In general, an insulation film with a high barrier height is used for the tunnel insulation film, for example, as is a silicon oxide film or a silicon oxynitride film. Specifically, it is general that an insulation film whose barrier height is equal to or greater than 3 eV is used. This is because, when data is maintained in the memory cell or when memory cell data is read, a tunnel current is precluded from flowing in the tunnel insulation film in a weak electric field applied to the tunnel insulation film. Specifically, this is because the tunnel current is precluded from flowing in the tunnel insulation film when the intensity of the electric field applied to the tunnel insulation film is equal to or smaller than about 5 MV/cm.
However, if the insulation film with its high barrier height described previously is used for the tunnel insulation film, the tunnel current hardly flows in the tunnel insulation film when data is written into the memory cell or when a strong electric field is applied to the tunnel insulation film in order to erase data contained in the memory cell. Specifically, even if the intensity of the electric field applied to the tunnel insulation film is equal to or greater than about 10 MV/cm, the tunnel current hardly flows in the tunnel insulation film. As a result, the time for writing data into the memory cell or an erase time has become lengthened.
In order to overcome such a problem, up to now, a high voltage has been applied to the control gate electrode. However, as downsizing of the memory cell or the like advances, a withstand voltage failure or the like of the tunnel insulation film responsive to a high voltage is more likely to occur. Specifically, in a memory cell fabricated under a design that is approximately 100 nm or smaller, it has been impossible to overcome the problem such as the withstand voltage failure of the tunnel insulation film.